| Kurzkommentar |
This is the counter part of the lecture ‚System Architecture‘ for multicore systems.
It builds on the material of lectures ’System Architecture' and on the lecture ‚Computer Architecture 1‘. Although we will summarize the material that we use, a student of this class should have heard at least one of these lectures or reserve substantial amounts of time for reading up on this material.
The class has three portions:
1) Hardware: the pipelined multi core processor from the computer architecture class is augmented with store buffers and operating system support: interrupts, multi level address translation, nested page tables, inter processor interrupts.
2) Structured Parallel C: A theory of store buffer reduction and order reduction is presented. This permits to define the semantics of structured parallel C (which uses a sequentially consistent memory model without store buffers) and to extend the C-compiler from the ‚System Achitecture‘ class for the translation of multiple C-threads
operating on a shared global memory and heap.
3) Hypervisor: In a nutshell a hypervisor is a kernel, whose guests are operating systems together with their user processes. Thus, in contrast to ordinary kernels the guests can run in translated mode. This is supported by memory management unit (MMUs) with nested page tables. Building on the kernel from the ‚System Architecture‘ lecture, we will outline the construction of a hypervisor for a multicore machine and its correctness proof.
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